Center for Signal and Information Processing (CSIP) Seminar

Speaker: Matthew D. Clark, Ph.D, NGMS Technical Fellow  - NGMS/SISRD/INS/MESOU

Title: Software Defined Radio: Motivation and State of the Art

Abstract: Software Defined Radio (SDR) has been, like many technologies, just around the corner, for many years. Recent advances in portability, modularity, and standards have moved SDR from the realm of single purpose, hobbyist, narrow bandwidth processors to multi-waveform , almost generic, processing engines. So much so, that if you can afford a rack of Zeon servers, you can move the processing stack to start directly at the output of the Analog-Digital Converter, and move the algorithm between platforms at will.  Now that this pure software portability has been achieved, what are the solutions for embedded systems that have limited Size, Weight and Power? Until recently, that answer has looked like custom ASICs or FPGAs, performing a single waveform, or at best, a single waveform family.  This hardware limitation doesn’t have to occur however. In engineering, a good rule of thumb is that the most difficult, or state of the art, attempt will always require customer logic / expensive development, but as capabilities increase, designers can afford to trade off implementation efficiency for ease of re-use and modularity. With the latest FPGAs available, the market has developed enough excess capacity that we can afford to be non-optimal in our efficiency, and thus make the equivalent of libraries in hardware that allow an algorithm to be implemented in SW or in HW. This talk will cover a short background in SDR and some of the open-source frameworks for SDR. We will examine some reasons (but not all) why it is important and some challenges. I will talk about REDHAWK, a US Government curated standard for SDR , and I will demonstrate the ADS-B waveform running on a laptop, in an laptop/FPGA and entirely in an FPGA; examining some of the trade offs.

Speakers Bio: Matthew Clark joined NGIT-TASC in 2007, with the goal of converting signal processing algorithms into embedded hardware and software. He holds a Ph.D. in Electrical and Computing Engineering from the Georgia Institute of Technology, focusing on the implementation of signal processing algorithms in hardware. He joined Northrop Grumman after 20 years with TRW, Hughes, Raytheon, Nortel, and Intel where he worked primarily in FPGA and ASIC design. While at Northrop Grumman, he has served as the Chief Engineer and/or program manager on a variety of IRaD and CRaD embedded signal processing programs. Matthew is currently working to define a canonical FPGA/embedded processing architecture for REDHAWK.

Event Details


  • Tuesday, August 28, 2018
    2:00 pm - Wednesday, August 29, 2018
    2:59 pm
Location: Room 5126, Centergy One Building

For More Information Contact

Motaz Alfarraj