Speaker: Jeff Dugger

Title: Adaptive Analog VLSI Signal Processing Systems and Neural Networks

Date: October 17, 2003

Time: 3:00 pm

Location: GCATT Room 325

Abstract:
While the digital world frantically pursues ever-faster clock speeds to satisfy demanding signal processing applications, a quiet revolution in analog computing has been brewing, which promises to do more with less
--- more sophisticated signal processing delivered at less power in a smaller space. Novel application of a digital memory technology, the floating-gate MOSFET (used in EEPROMs), as an analog memory and computation device provides the basic building block of this technology.
Utilization of inherent device physics provides the adaptivity and programmability needed to realize compact reconfigurable analog VLSI systems.
Floating-gate charge storage provides non-volatile memory for a matrix of coefficients, while the nonlinear current-voltage relation of the MOSFET provides signal-coefficient multiplication. Summation of products
is achieved simply using Kirckhoff's Current Law. Matrix coefficients adapt according to a correlation learning rule which utilizes physical device phenomena (electron tunneling and hot-electron injection) to program floating-gate charge. All of this functionality costs only four transistors per coefficient, each operating at nanowatts of power consumption. The resultant adaptive analog matrix-vector operations form the core of a novel analog VLSI signal-processing model, which is called
computing in memory. Peripheral circuitry determines learning behavior, controls programmability, and expands core matrix functionality.

Biography:

Jeff Dugger received his BSEE from Tennessee Technological University in 1993, and his MSEE from the Georgia Institute of Technology in 1996. He is interested in developing machine intelligence through learning. His
present research focuses on building adaptive analog VLSI circuits using floating-gate technology for continuous, on-chip learning systems.

Slides:

Speaker:	Jeff Dugger
Title:	Adaptive Analog VLSI Signal Processing Systems and Neural Networks
Date:	October 17, 2003
Time:	3:00 pm
Location:	GCATT Room 325
Abstract:	While the digital world frantically pursues ever-faster clock speeds to satisfy demanding signal processing applications, a quiet revolution in analog computing has been brewing, which promises to do more with less --- more sophisticated signal processing delivered at less power in a smaller space. Novel application of a digital memory technology, the floating-gate MOSFET (used in EEPROMs), as an analog memory and computation device provides the basic building block of this technology. Utilization of inherent device physics provides the adaptivity and programmability needed to realize compact reconfigurable analog VLSI systems. Floating-gate charge storage provides non-volatile memory for a matrix of coefficients, while the nonlinear current-voltage relation of the MOSFET provides signal-coefficient multiplication. Summation of products is achieved simply using Kirckhoff's Current Law. Matrix coefficients adapt according to a correlation learning rule which utilizes physical device phenomena (electron tunneling and hot-electron injection) to program floating-gate charge. All of this functionality costs only four transistors per coefficient, each operating at nanowatts of power consumption. The resultant adaptive analog matrix-vector operations form the core of a novel analog VLSI signal-processing model, which is called computing in memory. Peripheral circuitry determines learning behavior, controls programmability, and expands core matrix functionality.
Biography:	Jeff Dugger received his BSEE from Tennessee Technological University in 1993, and his MSEE from the Georgia Institute of Technology in 1996. He is interested in developing machine intelligence through learning. His present research focuses on building adaptive analog VLSI circuits using floating-gate technology for continuous, on-chip learning systems.
Slides: